The present invention relates to semiconductors and, more particularly, to stacking of device-bearing semiconductors.
For some time now, there has been a desire to increase the number of devices that can occupy a particular area on a circuit board in order to reduce the overall circuit board size. One of the ways that entities have approached doing so is by stacking packaged chips on top of one another. This is typically accomplished by use of an ancillary element, for example, a mini “circuit board” or “interposer” that two or more chips can connect to, or through use of flexible circuitry on a ribbon-like material that can wrap over or around one or more chips to affect the same result. These approaches connect to the chips from the top surfaces (i.e., at the points of connection) so the connecting material or interposer is parallel to the chips themselves. These two approaches achieve a smaller footprint, but do so at the expense of, for example added parasitic capacitance, noise or both. Moreover, such elements are always passive elements in that they cannot themselves include integrated circuit devices.
Thus, there is a need in the art for a better way of stacked packaging that does not require the use of such ancillary elements, is not restricted by the geometries and limited connectivity of the above approaches, or both.